This invention relates to integrated circuit chips, in particular, to a method and apparatus capable of reducing clock signal skew in an integrated circuit, between integrated circuits, and between integrated circuits and other circuits.
The timing of a microprocessor based circuit is controlled by one or more clock signals. A clock signal includes periodic transitions between high and low logic levels at high frequency. Early personal computers operated using clock signals with a frequency near 5 MHz, but current implementations use numerous clock sources with frequencies increasing towards 10 GHz.
The clock signal in a computer system is used for many purposes including to synchronize bus cycles in the system. Thus, all digital components in the computer system initiate data operations based upon the clock signal. Clock signals usually are generated by clock circuits and these clock circuits can be within an integrated circuit or fabricated on a printed circuit board. Microprocessor based circuits are often complex and include numerous electrical components, many of which are driven by a clock signal.
Referring to FIG. 1, a typical clock circuit 1 includes an oscillator circuit 2, which is typically crystal controlled, which is coupled to a clock buffer circuit 4. The oscillator circuit 2 generates a periodic signal at a predetermined frequency. A clock buffer circuit 4 receives the periodic signals from oscillator circuit 2 and generates multiple output clock signals. The output clock signals are produced by output buffers within clock buffer circuit 4. The clock signals are sent to multiple destination points D1, D2, D3, and D4 within an integrated circuit. The clock signals are then used to drive circuit components located at various sites across the integrated circuit.
Although occurring extremely rapidly, electrical signals require a finite amount of time to travel from one point to another on a circuit board. The longer the distance through which a signal must travel, the more time it takes for that signal to propagate the required distance. Conductive copper, or other conductive metal pathways, commonly called traces, are fabricated in an integrated circuit to provide conductive paths for signals to travel from one component to another. The length of the trace lengths between the output resistors Ro, of the clock buffer, and the various destination points often differs. For example, if the distance between resistor Ro and destination point D2 is shorter than the distance between resistor Ro and D4, it will take a clock signal longer to propagate to destination point D4 than D2. Thus, if the multiple clock signals are in phase at resistors Ro, and each destination point has a different associated trace length, then the clock signals arriving at the different destination points will be out of phase. This phase difference typically is referred to as clock skew.
Several attempts have been made to correct or reduce clock skew or delay. One technique, attempts to modify a circuit layout by adding additional trace length to the faster clock signal traces, to slow down the faster clock signals, so that all of the clock signals arrive substantially in phase at the destination points. However, this process is time consuming and expensive because of the extensive testing, fabrication, and subsequent modifications to form precise trace lengths to compensate for the clock signal skew. Another way to correct or reduce clock skew is to run the clock signals through delay circuits and adjust the delays for respective clock signals so that all clock signals arrive at their destination substantially in phase, which requires additional circuitry and delay xe2x80x9ctuningxe2x80x9d.
The problem with these attempts is that while they do mitigate clock skew to some extent, they fail to adequately address the effects caused by the inductance of the transmission lines. As advancing technologies increase line lengths and device switching speeds, the inductance effects of the transmission line starts to dominate the clock signal delay behavior. Therefore, to adequately address the problem of clock signal skew, the inductive transmission line effects must also be considered.
FIG. 2 illustrates a clock signal pathway which incorporates a signal source 5, a source output impedance Zs, and a low loss transmission line 6. The low loss transmission line 6 has an overall impedance Zo shown as line resistance RL, inductance LL, and capacitance CL. The low loss transmission line 6 begins at node N2 and terminates at node N3. Connected to node N3 is a termination line with a small capacitance CS.
As seen in FIG. 2, the voltage at node N1, is simply the input voltage which we will refer to as clock signal V1. The clock signal V1 is generated with an input source impedance Zs and is propagated to node N2. The signal at node N2 is divided due to the series connection of the source impedance Zs and the line impedance Zo. The signal at node N2 is V2. Signal V2 travels down the low loss transmission line 6 to node N3. Since there is a termination with a small capacitance CS connected to the low loss transmission line 6 the signal is reflected back through node N3. The signal V3 at node N3 is therefore double the initial value of V2 because the reflected signal is added to the incoming signal. The reflected signal is then sent back to N2 where it is also added to V2. Ultimately, the reflected signal travels to the source impedance Zs. Since the source impedance Zs is equal to the line impedance Zo there is no further reflection at the N2 end.
FIG. 3, is a graphical illustration of the input signal V1, the signal V2 at node N2, and the signal V3 at node N3 for a typical fast rising clock signal transmitted through the circuit in FIG. 2. The input clock signal V1 rises at a fast rate, 0 volts to 5 volts in about 10 pico-seconds (ps). The voltage V2 rises at half the rate of V1 because the V1 signal is divided at N2, as discussed above. The signal V2 levels off at a voltage of 2.5 Volts which is the point when V1 stops increasing, 5 Volts, this is indicated by the point B on the V2 line. The clock signal V3, rises at twice the rate as V2 because the reflected signal from the small capacitance termination end is added to the incoming signal at N3. The reflected signal is also sent back and finally reaches N2, represented as point A on the graph which then causes the signal V2 to rise at the same rate as V1 and V3.
As can be seen from FIG. 3, the first delay time T1, represents the time for signal V2 to propagate down the low loss transmission line 6 from node N2 to the node N3, where V3 starts, is about 40 ps. The second delay time T2, represent the time for the reflected signal to travel back across the low loss transmission line 6 from node N3 to node N2 which is also about 40 ps. Therefore, the total clock signal skew between V2 and V3 is the time it takes for the clock signal to travel down the low loss transmission line 6, from N2 to N3, a total of about 40 ps. On FIG. 3 the total skew is represented by the time of the first delay time T1. A skew this big or bigger is typical for a fast rising input clock signal along a low loss transmission line.
This type of clock skew is typically not addressed by conventional signal skew adjusting circuits.
The problems outlined above are in large part solved by the invention which reduces skew between clock signals by using low loss transmission lines in conjunction with a slow rising input clock signal.
As will be discussed in further detail below, when a slow rising clock signal is used in conjunction with a low loss transmission line 6 a period of time or region of no apparent skew or delay exists between the clock signals at the input and destination ends of the low loss transmission line 6. The signals with no apparent skew or delay can be used to operate various components within an integrated circuit.
The foregoing and other features and advantages of the invention will be more clearly understood from the following detailed description of the invention which is provided in conjunction with the accompanying drawings.